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ht9032c/ht9032d calling line identification receiver block diagram rev. 1.50 1 december 20, 2016 features operating voltage: 3.5v~5.5v bell 202 fsk and v.23 demodulation ring detection input and output carrier detection output power down mode high input sensitivity ht9032c: 16-pin sop package ht9032d: 8-pin dip/sop package applications feature phones caller id adjunct boxes fax and answering machines computer telephony interface products adsi products general description the ht9032 calling line identification receiver is a low power cmos integrated circuit designed for receiving physical layer signals transmitted according to bellcore tr-nwt-000030 and itu-t v.23 specifications. the primary application of this device is for products used to receive and display the calling number, or message waiting indicator sent to subscribers from the central of - fice facilities. the device also provides a carrier detec - tion circuit and a ring detection circuit for easier system applications.

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pin assignment pin description pin name i/o description power inputs vdd power-vdd is the input power for the internal logic. vss ground-vss is ground connection for the internal logic. pdwn i a logic 1 on this pin puts the chip in power down mode. when a logic 0 is on this pin, the chip in power up mode. this is a schmitt trigger input. clock x1 i a crystal or ceramic resonator should be connected to this pin and x2. this pin may be driven from an external clock source. x2 o a crystal or ceramic resonator should be connected to this pin and x1. ring detections rdet1 i it detects ring energy on the line through an attenuating network and enables the oscillator and ring detection. this is a schmitt trigger input. rdet2 i it couples the ring signal to the precision ring detector through an attenuating network. rdet =0 if a valid ring signal is detected. this is a schmitt trigger input. rtime i/o an rc network may be connected to this pin in order to hold the pin voltage below 2.2v be- tween the peaks of the ringing signal. this pin controls internal power up and activates the par- tial circuitry needed to determine whether the incoming ring is valid or not. the input is a schmitt trigger input. the output cell structure is an nmos output. fsk signal inputs tip i this input pin is connected to the tip side of the twisted pair wires. it is internally biased to 1/2 v dd when the device is in power up mode. this pin must be dc isolated from the line. ring i this input pin is connected to the ring side of the twisted pair wires. it is internally biased to 1/2 v dd when the device is in power up mode. this pin must be dc isolated from the line. detection results rdet o this open drain output goes low when a valid ringing signal is detected. when connected to pdwn pin, this pin can be used for auto power up. cdet o this open drain output goes low indicating that a valid carrier is present on the line. a hyster - esis is built-in to allow for a momentary drop out of the carrier. when connected to pdwn pin, this pin can be used for auto power up. dout o this pin presents the output of the demodulator when chip in power up mode. this data stream includes the alternate 1 and 0 pattern, the marking, and the data. at all other times, this pin is held high. doutc o this output presents the output of the demodulator when chip in power up mode and when an internal validation sequence has been successfully passed. this data stream does not include the alternate 1 and 0 pattern. this pin is always held high. test o output pin for testing purposes only. nc no connection ht9032c/ht9032d rev. 1.50 2 december 20, 2016 ' $ % ) $ $ * + & ( ' % % ' # $ $ + * $ &
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absolute maximum ratings voltages are referenced to v ss , except where noted. supply voltage ......................................... 0.5v to 6.0v all input voltages.................................................25mw operating temperature range ...................0 cto70 c storage temperature range ................ 40 cto150 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics crystal=3.58mhz, ta=0~70 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd supply voltage 3.5 5 5.5 v i dd1 supply current 5v pdwn=0 (3.58mhz osc on) 3.2 5 ma i dd2 supply current 5v pdwn=1 and rtime =0 (3.58mhz osc on and internal circuits partially on) 1.9 2.5 ma i stby standby current 5v pdwn=1 and rtime =1 (3.58mhz osc off) 1 a v il input voltage logic 0 5v 0.2v v dd v ih input voltage logic 1 5v 0.8v v dd i ol output voltage logic 0 5v i ol =1.6ma 0.1v v dd i oh output voltage logic 1 5v i oh =0.8ma 0.9v v dd i in input leakage current, all inputs 5v 1 1 a v t input low threshold voltage 5v rdet1, rtime , pdwn 2.0 2.3 2.6 v v t+ input high threshold voltage 5v rdet1, rtime , pdwn 2.5 2.75 3.0 v v trdet2 input threshold voltage 5v rdet2 1.0 1.1 1.2 v r in input dc resistance 5v tip, ring 500 k ht9032c/ht9032d rev. 1.50 3 december 20, 2016 ) $ $ * + & ( ' % % ' # $ $ + * $ & 4 , 5 . 1 ) 6 7 * 2 ) , 2 2 5 * %
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a.c. characteristics fsk detection v ss =0v, crystal=3.58mhz, ta=0 to 70 c, 0dbm=0.7746vrms @ 600 symbol parameter test conditions min. typ. max. unit v dd conditions input sensitivity: tip, ring 5v 40 45 dbm s/n signal to noise ratio 5v 20 db band pass filter 60hz 550hz 2700hz 3300hz 5v frequency response relative to 1700hz @ 0dbm 64 4 3 34 db carrier detect sensitivity 5v 48 dbm t dosc oscillator start up time 5v 2 ms t supd power up to fsk signal set up time 5v 15 ms t daq carrier detect acquisition time 5v 14 ms t dch end of data to carrier detect high 5v 8 ms ht9032c/ht9032d rev. 1.50 4 december 20, 2016
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ht9032c/ht9032d rev. 1.50 5 december 20, 2016 functional description the ht9032 is designed to be the physical layer de - modulator for products targeted for the caller id market. the data signaling interface should conform to bell 202, which is described as follows: analog, phase coherent, frequency shift keying logical 1 (mark)=1200+/ 12hz logical 0 (space)=2200+/ 22hz transmission rate=1200bps data application=serial, binary, asynchronous the interface should be arranged to allow simple data transmission from the terminating central office, to the cpe (customer premises equipment), only when the cpe is in an on-hook state. the data will be transmitted in the silent period between the first and second power ring before a voice path is established. the transmission level from the terminating c.o. will be 13.5dbm+/1.0. the worst case attenuation through the loop is expected to be 20db. the receiver therefore, should have a sen - sitivity of approximately 34.5dbm to handle the worst case installations. the itu-t v.23 is also using the fsk signaling scheme to transmit data in the general switched telephone network. for mode 2 of the v.23, the modulation rate and characteristic frequencies are listed below: analog, phase coherent, frequency shift keying logical 1 (mark)=1300hz logical 0 (space)=2100hz transmission rate=1200bps since the band pass filter of the ht9032 can pass the v.23 signal, hence the ht9032 also can demodulate the v.23 signal. ring detection the data will be transmitted in the silent period between the first and second power ring before a voice path is es - tablished. the ht9032 should first detect a valid ring and then perform the fsk demodulation. the typical ring detection circuit of the ht9032 is depicted below. the power ring signal is first rectified through a bridge circuit and then sent to a resistor network that attenu - ates the incoming power ring. the values of resistors and capacitor given in the figure have been chosen to provide a sufficient voltage at rdet1 pin to turn on the schmitt trigger input with approximately a 40 vrms or greater power ring input from tip and ring. when v t+ of the schmitt is exceeded, the nmos on the pin rtime will be driven to saturation discharging capacitor on rtime . this will initialize a partial power up, with only the portions of the part involved with the ring signal anal - ysis enabled, including rdet2 pin. with rdet2 pin en - abled, a portion of the power ring above 1.2v is fed to the ring analysis circuit. once the ring signal is qualified, the rdet pin will be sent low.

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operation mode there are three operation modes of the ht9032. they are power down mode, partial power up mode, and power up mode. the three modes are classified by the following conditions: modes conditions current consumption power down pdwn=1 and rtime =1 <1a partial power up pdwn=1 and rtime =0 1.9ma typically power up pdwn=0 3.2ma typically
application circuits application circuit 1 application circuit 2 ht9032c/ht9032d rev. 1.50 6 december 20, 2016 normally, the pdwn pin and the rtime pin control the operation mode of the ht9032. when both pins are high, the ht9032 is set at the power down mode, con - suming less than 1 a of supply current. when a valid power ring arrives, the rtime pin will be driven below v t- and the portions of the part involved in the ring signal analysis are enabled. this is partial power up mode, consuming approximately 1.9ma typically. once the pdwn pin is below v t- , the part will be fully powered up, and ready to receive fsk. during this mode, the device current will increase to approximately 3.2ma (typ). the state of the rtime pin is now a don t care as far as the part is concerned. after the fsk message has been re - ceived, the pdwn pin can be allowed to return to v dd and the part will return to the power down mode. 4 4 + & ( ' % % ' # + * , 5 . 1 ) 6 7 * 2 ) , 2 , 2 * . " * 1 " & 2 2 " 2 5 2 * - 0 2 " 2 5 2 * & 2 2 " 2 5 & ' # 2 5 & 2 5 * 3 4 4 ) $ $ * + & ( ' % % ' # $ $ + * $ & & 2 " & 2 " , 5 . 1 ) 6 7 * 2 ) , 2 , 2 & 0 2 " 2 5 & * . " * 1 " & 2 2 " 2 5 2 * - 0 2 " 2 5 2 * & 2 2 " 2 5 & ' # 2 5 & 2 5 * 3
application circuit 3 power on reset application circuit 4 power on reset note: reference c 1 =0.1fr 1 =81k ht9032c/ht9032d rev. 1.50 7 december 20, 2016 4 4 + & ( ' % % ' # + * , 5 . 1 ) 6 7 * 2 ) , 2 , 2 * . " * 1 " & 2 2 " 2 5 2 * - 0 2 " 2 5 2 * & 2 2 " 2 5 & ' # 2 5 & 2 5 * 3 * * 4 4 ) $ $ * + & ( ' % % ' # $ $ + * $ & & 2 " & 2 " , 5 . 1 ) 6 7 * 2 ) , 2 , 2 & 0 2 " 2 5 & * . " * 1 " & 2 2 " 2 5 2 * - 0 2 " 2 5 2 * & 2 2 " 2 5 & ' # 2 5 & 2 5 * 3 * * , 5 . 1 ) 6 7 < ( ' + * =
package information 8-pin dip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.355 0.365 0.400 b 0.240 0.250 0.280 c 0.115 0.130 0.195 d 0.115 0.130 0.150 e 0.014 0.018 0.022 f 0.045 0.060 0.070 g 0.100 bsc h 0.300 0.310 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 9.02 9.27 10.16 b 6.10 6.35 7.11 c 2.92 3.30 4.95 d 2.92 3.30 3.81 e 0.36 0.46 0.56 f 1.14 1.52 1.78 g 2.54 bsc h 7.26 7.87 8.26 i 10.92 ht9032c/ht9032d rev. 1.50 8 december 20, 2016 1 . - * $ # 6
8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010
08 symbol dimensions in mm min. nom. max. a 6.00 bsc b 3.90 bsc c 0.31 0.51 c 4.90 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25
08 ht9032c/ht9032d rev. 1.50 9 december 20, 2016 > # 6 $ 1 * - .
16-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.398 0.413 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013
08 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 10.11 10.49 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33
08 ht9032c/ht9032d rev. 1.50 10 december 20, 2016 * / * 3 1 $ # 6 >
ht9032c/ht9032d rev. 1.50 11 december 20, 2016 copyright 2016 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publica - tion. however, holtek assumes no responsibility arising from the use of the specifications de - scribed. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without fur - ther modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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